The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Aug. 16, 2022
Applicant:

Skyworks Solutions, Inc., Irvine, CA (US);

Inventors:

Hailing Wang, Acton, MA (US);

Dylan Charles Bartle, Arlington, MA (US);

Hanching Fuh, Allston, MA (US);

Jerod F. Mason, Bedford, MA (US);

David Scott Whitefield, Andover, MA (US);

Paul T. DiCarlo, Marlborough, MA (US);

Assignee:

SKYWORKS SOLUTIONS, INC., Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01); H03K 17/10 (2006.01); H03K 17/12 (2006.01); H03K 17/693 (2006.01); H01L 23/66 (2006.01); H01L 27/12 (2006.01); H04B 1/38 (2015.01);
U.S. Cl.
CPC ...
H03K 17/161 (2013.01); H01L 23/66 (2013.01); H01L 27/1203 (2013.01); H03K 17/102 (2013.01); H03K 17/122 (2013.01); H03K 17/693 (2013.01); H01L 2223/6677 (2013.01); H03K 2217/0018 (2013.01); H04B 1/38 (2013.01);
Abstract

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.


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