The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2023
Filed:
Apr. 29, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Hao-I Yang, Hsinchu, TW;
Cheng Hung Lee, Hsinchu, TW;
Chen-Lin Yang, Hsinchu, TW;
Chiting Cheng, Hsinchu, TW;
Fu-An Wu, Hsinchu, TW;
Yangsyu Lin, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A clock circuit includes a latch circuit, a memory state latch circuit, a first inverter, a memory state trigger circuit and a second inverter. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal and a first output clock signal. The memory state latch circuit is configured to latch a second output clock signal responsive to a third output clock signal. The first inverter is configured to generate the first output clock signal responsive to the third output clock signal. The memory state trigger circuit is configured to generate the second output clock signal responsive to the latch output signal. The second inverter is configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.