The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Jul. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Bey Wu, Hsinchu, TW;

Dian-Hau Chen, Hsinchu, TW;

Jye-Yen Cheng, Taichung, TW;

Sheng-Hsuan Wei, Taoyuan, TW;

Li-Yu Lee, New Taipei, TW;

Tai-Yang Wu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); G06F 30/392 (2020.01); H01L 21/31144 (2013.01); H01L 21/7682 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5222 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01);
Abstract

A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.


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