The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Apr. 04, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Shinn-Sheng Yu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G03F 1/36 (2012.01); G03F 7/20 (2006.01); G03F 7/00 (2006.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G03F 1/36 (2013.01); G03F 7/70441 (2013.01);
Abstract

A method of enhancing a layout pattern includes determining a target layout pattern comprising a disk shape associated with a hole. The method includes defining a polygon having a plurality of vertices on the disk shape. The plurality of vertices coincide with a boundary of the disk shape and the polygon is an initial layout pattern of the hole. The method includes performing an iterative correction of the initial layout pattern. The iterative correction includes projecting the layout pattern of the hole onto a substrate, determining an error between the target layout pattern and the projected layout pattern, and adjusting the layout pattern by moving the vertices of the polygon to generate a next iteration of the layout pattern. The method includes continuing the adjusting, projecting, and determining until a criterion is satisfied and a final iteration of the layout pattern of the hole is generated.


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