The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2023
Filed:
Jul. 30, 2021
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Fu An Tien, Hsinchu, TW;
Hsu-Ting Huang, Hsinchu, TW;
Ru-Gun Liu, Zhubei, TW;
Shih-Hsiang Lo, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/398 (2020.01); G03F 7/00 (2006.01); G01N 21/95 (2006.01); G03F 1/36 (2012.01); G06F 30/3308 (2020.01); G06F 30/337 (2020.01); G06F 119/18 (2020.01); G03F 1/70 (2012.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G01N 21/9503 (2013.01); G03F 1/36 (2013.01); G03F 7/70441 (2013.01); G06F 30/337 (2020.01); G06F 30/3308 (2020.01); G03F 1/70 (2013.01); G03F 7/705 (2013.01); G03F 7/70633 (2013.01); G06F 30/30 (2020.01); G06F 2119/18 (2020.01);
Abstract
In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.