The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Feb. 25, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Harry-Hak-Lay Chuang, Zhubei, TW;

Wei Cheng Wu, Zhubei, TW;

Ya-Chen Kao, Fuxing Township, TW;

Yi Hsien Lu, Yuanchang Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/40 (2023.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 27/11573 (2017.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11573 (2013.01); H01L 21/823462 (2013.01); H01L 27/092 (2013.01); H01L 29/42344 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/665 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 27/088 (2013.01);
Abstract

The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.


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