The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Aug. 10, 2022
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chung-Yen Feng, Hsinchu County, TW;

Chen-An Kuo, Taoyuan, TW;

Ching-Wei Teng, Taoyuan, TW;

Po-Chun Lai, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/285 (2006.01); H01L 21/74 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/28518 (2013.01); H01L 21/743 (2013.01); H01L 29/1087 (2013.01); H01L 29/1095 (2013.01); H01L 29/45 (2013.01); H01L 29/66681 (2013.01);
Abstract

An LDMOS includes a semiconductor substrate. A well is disposed within the semiconductor substrate. A body region is disposed within the well. A first gate electrode is disposed on the semiconductor substrate. A source electrode is disposed at one side of the first gate electrode. The source electrode includes a source contact area and numerous vias. The vias connect to the source contact area. The vias extend into the semiconductor substrate. A first drain electrode is disposed at another side of the first gate electrode and is opposed to the source electrode.


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