The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Jul. 09, 2020
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chia-Liang Liao, Yunlin County, TW;

Purakh Raj Verma, Singapore, SG;

Ching-Yang Wen, Pingtung County, TW;

Chee Hau Ng, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 21/48 (2006.01); H01L 23/15 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); H01L 21/4871 (2013.01); H01L 23/15 (2013.01); H01L 23/3736 (2013.01);
Abstract

A semiconductor structure includes a glass substrate and a device wafer. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.


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