The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Dec. 18, 2020
Applicant:

Psemi Corporation, San Diego, CA (US);

Inventors:

Jacob Hamilton, San Diego, CA (US);

Tran Kononova, San Diego, CA (US);

Jay Kothari, San Diego, CA (US);

Matt Allison, Oceanside, CA (US);

Kim T. Nguyen, San Diego, CA (US);

Eric S. Shapiro, San Diego, CA (US);

Assignee:

PSEMI CORPORATION, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 23/00 (2006.01); G01R 31/28 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); G01R 31/2884 (2013.01); H01L 23/562 (2013.01); H01L 23/564 (2013.01); H01L 23/585 (2013.01);
Abstract

Method and devices to reduce integrated circuit fabrication process yield loss due to undesired interactions between PCMs and the wafer test probes during wafer sorting tests are disclosed. The described methods entail the use of a properly patterned metal layer on the PCM dies adjacent to the product dies under test. Such patterned metal layers shield traces of the wafer probes from the circuits of the PCM dies. Various exemplary metal layer patterns are also presented.


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