The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Jul. 30, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chin-Shen Lin, Taipei, TW;

Wan-Yu Lo, Taoyuan County, TW;

Shao-Huan Wang, Taichung, TW;

Kuo-Nan Yang, Hsinchu, TW;

Chung-Hsing Wang, Hsinchu County, TW;

Sheng-Hsiung Chen, Hsinchu County, TW;

Huang-Yu Chen, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/392 (2020.01); G06F 30/347 (2020.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/347 (2020.01); H01L 21/78 (2013.01);
Abstract

A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.


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