The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

May. 12, 2021
Applicant:

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Janbo Zhang, Zhangzhou, CN;

Chao-Wei Lin, Hsinchu County, TW;

Chia-Yi Chu, Hsinchu, TW;

Yu-Cheng Tung, Kaohsiung, TW;

Ken-Li Chen, Taoyuan, TW;

Tsung-Wen Chen, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H10B 12/315 (2023.02); H01L 23/5329 (2013.01); H10B 12/482 (2023.02); H10B 12/488 (2023.02);
Abstract

A semiconductor memory device is provided in the present invention, including a substrate, word lines in the substrate, bit lines over the word lines, partition structures between the bit lines and right above the word lines, storage node contacts in spaces defined by the bit lines and the partition structures and electrically connecting with the substrate, wherein a portion of the storage node contact protruding from top surfaces of the bit lines and the partition structures is contact pad, and contact pad isolation structures on the partition structures and between the contact pads, wherein the contact pad isolation structure includes outer silicon nitride layers and inner silicon oxide layers.


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