The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Oct. 30, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Pratik A. Patel, Portland, OR (US);

Mark Y. Liu, West Linn, OR (US);

Jami A. Wiedemer, Beaverton, OR (US);

Paul A. Packan, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/225 (2006.01); H01L 21/324 (2006.01); H01L 29/08 (2006.01); H01L 29/24 (2006.01); H01L 29/267 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/2253 (2013.01); H01L 21/324 (2013.01); H01L 29/0847 (2013.01); H01L 29/24 (2013.01); H01L 29/267 (2013.01); H01L 29/66492 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/66803 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01);
Abstract

A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.


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