The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Sep. 02, 2021
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventor:

Hung-Yu Wei, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4236 (2013.01); G11C 11/4085 (2013.01); H10B 12/05 (2023.02); H10B 12/34 (2023.02); H10B 12/488 (2023.02);
Abstract

A dynamic random access memory includes a substrate, an isolation structure, and a buried word line structure. The isolation structure is located in the substrate and defines multiple active regions. The buried word line structure is located in a word line trench in the substrate, and the word line trench passes through the active regions and the isolation structure. The buried word line structure includes a gate conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The gate conductive layer is located in the word line trench. The first gate dielectric layer is located on a sidewall and a bottom surface of the word line trench. The second gate dielectric layer is located between the first gate dielectric layer and the gate conductive layer, and a top surface of the second gate dielectric layer is lower than a top surface of the gate conductive layer.


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