The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Aug. 25, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

David Wolpert, Poughkeepsie, NY (US);

Ryan Michael Kruse, Williamson, TX (US);

Leon Sigal, Monsey, NY (US);

Richard Edward Serton, Charlottesville, VA (US);

Matthew Stephen Angyal, Stormville, NY (US);

Terence Hook, Jericho Center, VT (US);

Richard Andre Wachnik, Mount Kisco, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/394 (2020.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); H01L 27/0207 (2013.01);
Abstract

Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.


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