The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Jul. 31, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventor:

Shyh-Shin Ferng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/11 (2006.01); H01L 29/66 (2006.01); H01L 27/146 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78618 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/28518 (2013.01); H01L 21/30604 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01);
Abstract

Gate-all-around (GAA) devices and methods of manufacturing such devices are described herein. A method includes forming a multi-layer structure over a substrate and forming a plurality of source/drain regions in the multi-layer structure. Fins are then patterned into the multi-layer structure through adjacent source/drain regions. A wire release process is performed to remove materials of one or more of the layers in the multi-layer stack. The remaining layers of the multi-layer stack form a stack of nanostructures connecting adjacent source/drain regions of the fins.


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