The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Dec. 31, 2018
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Sunglyong Kim, Allen, TX (US);

Seetharaman Sridhar, Richardson, TX (US);

Hong Yang, Richardson, TX (US);

Ya Ping Chen, Chengdu, CN;

Thomas Eugene Grebs, Bethlehem, PA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/872 (2006.01); H01L 21/8234 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/823437 (2013.01); H01L 21/823487 (2013.01); H01L 27/088 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01); H01L 29/872 (2013.01);
Abstract

An integrated circuit includes a trench gate MOSFET including MOSFET cells. Each MOSFET cell includes an active trench gate in an n-epitaxial layer oriented in a first direction with a polysilicon gate over a lower polysilicon portion. P-type body regions are between trench gates and are separated by an n-epitaxial region. N-type source regions are located over the p-type regions. A gate dielectric layer is between the polysilicon gates and the body regions. A metal-containing layer contacts the n-epitaxial region to provide an anode of an embedded Schottky diode. A dielectric layer over the n-epitaxial layer has metal contacts therethrough connecting to the n-type source regions, to the p-type body regions, and to the anode of the Schottky diode.


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