The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Nov. 26, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Neha Gholkar, Milipitas, CA (US);

Akhilesh Kumar, Saratoga, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0891 (2016.01); G06F 12/121 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0891 (2013.01); G06F 12/121 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/60 (2013.01);
Abstract

Disclosed embodiments relate to a cache line eviction algorithm. In one example, a system includes a last level cache (LLC) having multiple ways, each allocated to one of multiple priorities, each having specified minimum and maximum ways to occupy, a cache control circuit (CCC) to store an incoming cache line (CL) having a requestor priority to an invalid CL, if any, otherwise, when the requestor priority is a lowest priority and has an occupancy of one or more, or when the occupancy is at a maximum, to evict a least recently used (LRU) CL of the requestor priority, otherwise, when the occupancy is between a minimum and a maximum, to evict a LRU CL of the requestor or a lower priority, otherwise, when the occupancy is less than the minimum, to evict a LRU CL, if any, of the lower priority, and otherwise, to evict a LRU CL of a higher priority.


Find Patent Forward Citations

Loading…