The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Oct. 27, 2021
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Chia-Jung Hsu, Tainan, TW;

Chin-Hung Chen, Tainan, TW;

Chun-Ya Chiu, Tainan, TW;

Chih-Kai Hsu, Tainan, TW;

Ssu-I Fu, Kaohsiung, TW;

Tsai-Yu Wen, Tainan, TW;

Shi You Liu, Kaohsiung, TW;

Yu-Hsiang Lin, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 21/265 (2006.01); H01L 29/167 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/105 (2013.01); H01L 21/26506 (2013.01); H01L 29/0649 (2013.01); H01L 29/167 (2013.01);
Abstract

A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.


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