The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Jun. 24, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chang-Fen Hu, Hsinchu, TW;

Shao-Yu Li, Hsinchu, TW;

Kuo-Ji Chen, Taipei County, TW;

Chih-Peng Lin, Hsinchu, TW;

Chuei-Tang Wang, Taichung, TW;

Ching-Fang Chen, Taichung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 25/065 (2023.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 23/5383 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 25/0657 (2013.01);
Abstract

A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a PMOS transistor and an NMOS transistor. A first source/drain region of the PMOS transistor may be connected to a first source/drain region of the NMOS transistor and the die-to-die interconnect.


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