The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Feb. 04, 2021
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Min-Shiang Hsu, Kaohsiung, TW;

Yu-Han Tsai, Kaohsiung, TW;

Chih-Sheng Chang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 21/033 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/0332 (2013.01); H01L 21/7684 (2013.01); H01L 21/76816 (2013.01); H01L 21/76832 (2013.01); H01L 21/76879 (2013.01); H01L 21/76897 (2013.01); H01L 23/5283 (2013.01);
Abstract

The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a first inter metal dielectric (IMD) layer, a second inter metal dielectric layer and a third inter metal dielectric layer sequentially arranged on the substrate. The first inter metal dielectric layer includes at least one first wire, the second inter metal dielectric layer includes at least one mask layer, and the third inter metal dielectric layer includes at least one third wire and a super via. The super via penetrates through the second inter metal dielectric layer, and electrically connect to the first wire and the third wire, and part of the super via directly contacts the mask layer in the second inter metal dielectric layer.


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