The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Dec. 28, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shahaji B. More, Hsinchu, TW;

Zheng-Yang Pan, Zhubei, TW;

Cheng-Han Lee, New Taipei, TW;

Shih-Chieh Chang, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 21/285 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/02532 (2013.01); H01L 21/28518 (2013.01); H01L 21/76802 (2013.01); H01L 21/76889 (2013.01); H01L 21/823418 (2013.01); H01L 29/41791 (2013.01); H01L 29/45 (2013.01); H01L 29/665 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 21/76843 (2013.01); H01L 21/76855 (2013.01); H01L 21/823814 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01);
Abstract

A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.


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