The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Jul. 19, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Foroozan S. Koushan, San Jose, CA (US);

Shinji Sato, Kanagawa, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/32 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/32 (2013.01);
Abstract

Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first select line of the data block and a second voltage signal to be applied to a second select line of the data block, wherein the first select line is coupled to a first device in the string of memory cells and the second select line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation. The control logic further determines an end of the first stage of the erase operation and causes the first voltage signal to decrease to a second voltage offset with respect to the erase voltage signal and causes the second voltage signal to decrease to a third voltage offset with respect to the erase voltage signal during a second stage of the erase operation, wherein the second offset is greater than the third offset.


Find Patent Forward Citations

Loading…