The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2023

Filed:

Feb. 14, 2022
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Wei-Liang Lin, Taipei, TW;

Wen-Jer Tsai, Hualien, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 21/762 (2006.01); H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/28 (2006.01); H01L 29/788 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 21/0223 (2013.01); H01L 21/02164 (2013.01); H01L 21/02636 (2013.01); H01L 21/31116 (2013.01); H01L 21/32051 (2013.01); H01L 21/32055 (2013.01); H01L 21/32135 (2013.01); H01L 21/76224 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/42324 (2013.01); H01L 29/7883 (2013.01); H01L 29/7884 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H01L 21/02255 (2013.01);
Abstract

A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.


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