The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2023

Filed:

May. 28, 2021
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Kuan-Hsiang Mao, Kaohsiung, TW;

Wen Hung Huang, Kaohsiung, TW;

Che Ming Fang, Kaohsiung, TW;

Yufu Liu, Kaohsiung, TW;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); C09D 5/24 (2006.01); C09D 179/04 (2006.01); C09D 179/08 (2006.01); G03F 7/09 (2006.01);
U.S. Cl.
CPC ...
H01L 24/03 (2013.01); C09D 5/24 (2013.01); C09D 179/04 (2013.01); C09D 179/08 (2013.01); H01L 24/02 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); G03F 7/09 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0362 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/13026 (2013.01);
Abstract

A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device () having conductive patterns () disposed on a first surface and then forming, on the conductive patterns, photoresist islands () having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer () surrounds but does not cover each photoresist island (), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings () in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.


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