The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2023

Filed:

Dec. 20, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nicholas Neal, Gilbert, AZ (US);

Divya Mani, Chandler, AZ (US);

Nicholas Haehn, Scottsdale, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/473 (2006.01); H01L 23/498 (2006.01); H01L 23/467 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/473 (2013.01); H01L 21/481 (2013.01); H01L 21/4846 (2013.01); H01L 21/4871 (2013.01); H01L 23/467 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01);
Abstract

An integrated circuit assembly may be formed having a substrate core, wherein the substrate core includes at least one heat transfer fluid channel formed therein, a first build-up layer formed on a first surface of the substrate core, and a second build-up layer formed on a second surface of the substrate core, and methods of fabricating the same. In embodiments of the present description, the integrated circuit structure may include at least one integrated circuit device formed within at least one of the first build-up layer and the second build-up layer. The embodiments of the present description allow for cooling within the substrate, which may significantly reduce thermal damage to the components of the substrate and/or integrated circuit devices within the substrate.


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