The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2023

Filed:

Jul. 09, 2021
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Michael L. Takefman, Nepean, CA;

Maher Amer, Nepean, CA;

Claus Reitlingshoefer, Kanata, CA;

Riccardo Badalone, St. Lazare, CA;

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G11C 7/10 (2006.01); G11C 5/04 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1012 (2013.01); G11C 5/04 (2013.01); G11C 7/106 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01);
Abstract

A system and method are directed to providing a configurable timing control of a memory system. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flipflops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.


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