The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

May. 11, 2021
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Che-Fu Chuang, Taichung, TW;

Hsiu-Han Liao, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/40 (2023.01); H10B 41/49 (2023.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H10B 41/40 (2023.02); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/32134 (2013.01); H01L 21/32139 (2013.01);
Abstract

A method for fabricating a semiconductor device includes: forming a first gate dielectric layer in a first and a second regions of a peripheral region of a substrate; forming a first conductive layer and a first hard mask layer over the substrate; forming a first mask layer on the first hard mask layer in the first region; removing the first hard mask layer outside the first region; removing the first hard mask layer; performing a wet etch process by taking the first hard mask layer as a mask, and removing the first conductive layer and the first gate dielectric layer outside the first region; removing the first hard mask layer and the first conductive layer; forming a second gate dielectric layer in the second region; and forming a first and a second gate conductive layers in the first and the second regions respectively.


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