The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Oct. 28, 2020
Applicant:

Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;

Inventors:

Chien-Hua Chen, Kaohsiung, TW;

Teck-Chong Lee, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 23/522 (2006.01); H01L 23/64 (2006.01); H01L 23/14 (2006.01); H01L 23/15 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 28/10 (2013.01); H01L 23/522 (2013.01); H01L 23/5223 (2013.01); H01L 23/5227 (2013.01); H01L 23/147 (2013.01); H01L 23/15 (2013.01); H01L 23/642 (2013.01); H01L 23/645 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/0362 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/13111 (2013.01); H01L 2924/14 (2013.01);
Abstract

A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.


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