The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2023
Filed:
May. 20, 2021
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Hidehiro Fujiwara, Hsinchu, TW;
Chih-Yu Lin, Hsinchu, TW;
Hsien-Yu Pan, Hsinchu, TW;
Yasutoshi Okuno, Hsinchu, TW;
Yen-Huei Chen, Hsinchu, TW;
Hung-Jen Liao, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The memory circuit is a four transistor memory cell that includes at least the first pass gate transistor and the first pull up transistor. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull up transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact is electrically coupled to a source of the first pull up transistor. The first metal contact layout pattern extends in a second direction, overlaps a cell boundary of the memory circuit and the first active region layout pattern.