The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Sep. 14, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Sheng-Chieh Chen, Taichung, TW;

Chih-Ren Hsieh, Changhua, TW;

Ming-Lun Lee, Hsinchu, TW;

Wei-Ming Wang, Taichung, TW;

Ming Chyi Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11524 (2017.01); H01L 29/423 (2006.01); H01L 23/29 (2006.01); H01L 27/11534 (2017.01); H01L 27/11548 (2017.01); H01L 27/11529 (2017.01); H01L 29/417 (2006.01); H01L 21/56 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 21/28 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/291 (2013.01); H01L 21/56 (2013.01); H01L 23/3192 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11534 (2013.01); H01L 27/11548 (2013.01); H01L 29/40114 (2019.08); H01L 29/41775 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01);
Abstract

A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.


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