The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2023

Filed:

Mar. 13, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David J. Harriman, Portland, OR (US);

Debendra Das Sharma, Saratoga, CA (US);

Daniel S. Froelich, Portland, OR (US);

Sean O. Stalley, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/14 (2006.01); G06F 13/42 (2006.01); H04B 1/7073 (2011.01); H04L 69/14 (2022.01);
U.S. Cl.
CPC ...
G06F 1/14 (2013.01); G06F 13/4221 (2013.01); H04B 1/7073 (2013.01); G06F 2213/0026 (2013.01); H04B 2201/7073 (2013.01); H04B 2201/70718 (2013.01); H04L 69/14 (2013.01);
Abstract

Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.


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