The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Aug. 05, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yu-I Shih, Taichung, TW;

Ren-Hua Guo, Taichung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/11 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 21/3065 (2006.01); H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/02293 (2013.01); H01L 21/3065 (2013.01); H01L 21/823821 (2013.01); H01L 29/045 (2013.01); H01L 29/165 (2013.01); H01L 29/66795 (2013.01); H01L 29/7853 (2013.01); H01L 29/7854 (2013.01);
Abstract

A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer.


Find Patent Forward Citations

Shih, Yu-I. (2023). Semiconductor device and manufacturing method thereof (U.S. Patent No. 11621268). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11621268

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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