The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Jan. 29, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Brent Keeth, Boise, ID (US);

Bambi L. DeLaRosa, Frisco, TX (US);

Eiichi Nakano, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G06F 3/06 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H01L 21/00 (2006.01); G11C 29/00 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); G11C 5/06 (2013.01); H01L 21/00 (2013.01); H01L 25/18 (2013.01); G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G11C 29/006 (2013.01); H01L 27/108 (2013.01);
Abstract

Techniques for wafer-scale memory device and systems are provided. In an example, a wafer-scale memory device can include a large single substrate, multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate, and multiple streets separating the memory circuit areas. The streets can accommodate attaching the substrate to a wafer-scale processor. In certain examples, the large, single substrate can have a major surface area of more than 20,000 square millimeters (mm).


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