The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2023
Filed:
Apr. 30, 2021
Applicant:
Dialog Semiconductor (Uk) Limited, London, GB;
Inventors:
Assignee:
Dialog Semiconductor (UK) Limited, London, GB;
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 21/565 (2013.01); H01L 23/49866 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73207 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/3511 (2013.01);
Abstract
A single-side stack up system in package is described. The system in package comprises a first interconnection having redistribution layers therein and having a top surface and a bottom surface, at least one first silicon die mounted on the top surface of the first interconnection and embedded in a first molding compound, at least one first passive component mounted on the top surface of the first interconnection side-by-side with the at least one first silicon die and embedded in a second molding compound, and solder balls mounted on the bottom surface of the first interconnection wherein the solder balls provide package output.