The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Jul. 16, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Nicholas Anthony Lanzillo, Wynantskill, NY (US);

Hosadurga Shobha, Niskayuna, NY (US);

Junli Wang, Slingerlands, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Christopher J. Penny, Saratoga Springs, NY (US);

Robert Robison, Rexford, NY (US);

Huai Huang, Clifton Park, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76844 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76849 (2013.01); H01L 21/76865 (2013.01); H01L 21/76879 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01);
Abstract

A method for fabricating a semiconductor device includes forming one or more layers including at least one of a liner and a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench, after forming the one or more liners, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level, and forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material.


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