The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2023
Filed:
Mar. 24, 2020
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Heng Wu, Guilderland, NY (US);
Ruilong Xie, Niskayuna, NY (US);
Su Chen Fan, Cohoes, NY (US);
Jay William Strane, Warwick, NY (US);
Hemanth Jagannathan, Niskayuna, NY (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/265 (2013.01); H01L 21/823885 (2013.01); H01L 27/092 (2013.01); H01L 29/0653 (2013.01); H01L 29/6656 (2013.01); H01L 29/7827 (2013.01);
Abstract
A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.