The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Dec. 30, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Jiangang Wu, Boise, ID (US);

Qisong Lin, Boise, ID (US);

Jung Sheng Hoei, Boise, ID (US);

Yunqiu Wan, Boise, ID (US);

Ashutosh Malshe, Boise, ID (US);

Peng-Cheng Chen, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 12/0891 (2016.01); G06F 12/0811 (2016.01); G06F 12/02 (2006.01); G06F 12/0882 (2016.01); G06F 11/14 (2006.01); G11C 16/06 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0891 (2013.01); G06F 11/14 (2013.01); G06F 12/0246 (2013.01); G06F 12/0811 (2013.01); G06F 12/0882 (2013.01); G06F 13/1668 (2013.01); G11C 16/06 (2013.01);
Abstract

Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.


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