The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2023

Filed:

Dec. 02, 2020
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Ching Hung Wang, Hsinchu, TW;

Shih Chin Lee, Taichung, TW;

Chen-Yu Cheng, Hsinchu, TW;

Tzung-Ting Han, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/11556 (2017.01); H01L 21/768 (2006.01); H01L 27/11582 (2017.01); H01L 27/11573 (2017.01); H01L 27/11529 (2017.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01);
Abstract

Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.


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