The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Feb. 26, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Wei Chen, Hsinchu, TW;

Wei Cheng Hsu, Hsinchu, TW;

Hui-Chi Chen, Hsinchu County, TW;

Jian-Hao Chen, Hsinchu, TW;

Kuo-Feng Yu, Hsinchu County, TW;

Shih-Hang Chiu, Taichung, TW;

Wei-Cheng Wang, Hsinchu, TW;

Yen-Ju Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 27/092 (2006.01); H01L 29/786 (2006.01); H01L 29/49 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); H01L 21/823828 (2013.01); H01L 27/092 (2013.01); H01L 29/42376 (2013.01); H01L 29/4966 (2013.01); H01L 29/78696 (2013.01);
Abstract

The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.


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