The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Jun. 21, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Henry Chin, Fremont, CA (US);

Hua-Ling Hsu, Fremont, CA (US);

Liang Li, Shanghai, CN;

Xuan Tian, Shanghai, CN;

Fanglin Zhang, Fremont, CA (US);

Guanhua Yin, Shanghai, CN;

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3427 (2013.01); G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01);
Abstract

Countermeasure method for programming a non-defective plane of a non-volatile memory experiencing a neighbor plane disturb, comprising, once a first plane is determined to have completed programming of a current state but where not all planes have completed the programming, a loop count is incremented and a determination is made as to whether the loop count exceeds a threshold. If so, programming of the incomplete plane(s) is ceased and programming of the completed plane(s) is resumed by suspending the loop count and bit scan mode, and, on a next program pulse, applying a pre-determined rollback voltage to decrement a program voltage bias. The loop count and bit scan mode are resumed once a threshold voltage level equals a program voltage bias when the loop count was last incremented. BSPF criterion is applied for each programmed state. Advancement to the next loop only occurs if a programmed state is determined incomplete.


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Chin, Henry. (2023). Countermeasure modes to address neighbor plane disturb condition in non-volatile memory structures (U.S. Patent No. 11605436). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11605436

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