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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11600618 B1

PDFFull Text
Date of Patent:
Mar. 07, 2023

Filed:

Mar. 18, 2021

Integrated circuit structure and manufacturing method thereof

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Harry-Hak-Lay Chuang, Hsinchu County, TW;

Li-Feng Teng, Hsinchu, TW;

Wei-Cheng Wu, Hsinchu County, TW;

Fang-Lan Chu, Taichung, TW;

Ya-Chen Kao, Taoyuan, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Maschoff Brennan

Primary Examiner:

Karen Kusumakar

Assistant Examiner:

Adam S Bowen

Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/28088 (2013.01); H01L 21/82385 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/41791 (2013.01); H01L 29/42376 (2013.01); H01L 29/4966 (2013.01); H01L 29/6656 (2013.01); H01L 29/66492 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/7833 (2013.01); H01L 29/7851 (2013.01); H01L 27/1104 (2013.01);
Abstract

A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.

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