The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Dec. 07, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chun-Yi Lee, Hsinchu, TW;

Hong-Hsien Ke, Changhua County, TW;

Chung-Ting Ko, Kaohsiung, TW;

Chia-Hui Lin, Dajia Township, TW;

Jr-Hung Li, Chupei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); C23C 16/34 (2006.01); C23C 16/455 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823468 (2013.01); C23C 16/345 (2013.01); C23C 16/45542 (2013.01); H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/02211 (2013.01); H01L 21/31116 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01);
Abstract

An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.


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