The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Oct. 12, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Juan J. Noguera Serra, San Jose, CA (US);

Sneha Bhalchandra Date, San Jose, CA (US);

Jan Langer, Chemnitz, DE;

Baris Ozgul, Dublin, IE;

Goran Hk Bilski, Molndal, SE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 15/177 (2006.01); G06F 15/80 (2006.01); G06F 15/173 (2006.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 15/177 (2013.01); G06F 15/17306 (2013.01); G06F 15/80 (2013.01); G06F 9/4401 (2013.01); G06F 9/4411 (2013.01);
Abstract

A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.


Find Patent Forward Citations

Loading…