The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2023

Filed:

Apr. 01, 2021
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Yong Liu, Cumberland Foreside, ME (US);

Yusheng Lin, Phoenix, AZ (US);

Huibin Chen, Suzhou, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/532 (2006.01); H01L 23/373 (2006.01); H01L 21/56 (2006.01); H01L 25/07 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 24/33 (2013.01); H01L 21/565 (2013.01); H01L 23/3735 (2013.01); H01L 23/53238 (2013.01); H01L 25/0655 (2013.01); H01L 23/645 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 25/072 (2013.01); H01L 2224/97 (2013.01);
Abstract

In a general aspect, a method for producing a semiconductor device assembly can include defining a cavity in a conductive spacer, and electrically and thermally coupling a semiconductor die with the conductive spacer, such that the semiconductor die is at least partially embedded in the cavity. The semiconductor die can have a first surface having active circuitry included therein, a second surface opposite the first surface, and a plurality of side surfaces each extending between the first surface of the semiconductor die and the second surface of the semiconductor die. The method can also include electrically coupling a direct bonded metal (DBM) substrate with the first surface of the semiconductor die.


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