The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2023

Filed:

Dec. 21, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kwang Soo Seol, Yongin-si, KR;

Chanjin Park, Yongin-si, KR;

Kihyun Hwang, Seongnam-si, KR;

Hanmei Choi, Seoul, KR;

Sunghoi Hur, Seoul, KR;

Wansik Hwang, Hwaseong-si, KR;

Toshiro Nakanishi, Seongnam-si, KR;

Kwangmin Park, Seoul, KR;

Juyul Lee, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 29/423 (2006.01); H01L 21/3213 (2006.01); H01L 27/06 (2006.01); H01L 27/11551 (2017.01); H01L 27/11556 (2017.01); H01L 27/11578 (2017.01); H01L 29/792 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 29/42348 (2013.01); H01L 21/32137 (2013.01); H01L 27/0688 (2013.01); H01L 27/11551 (2013.01); H01L 27/11556 (2013.01); H01L 27/11578 (2013.01); H01L 27/11582 (2013.01); H01L 29/511 (2013.01); H01L 29/517 (2013.01); H01L 29/792 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.


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