The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2023

Filed:

May. 27, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kishore K. Muchherla, Fremont, CA (US);

Ashutosh Malshe, Fremont, CA (US);

Preston A. Thomson, Boise, ID (US);

Michael G. Miller, Boise, ID (US);

Sampath K. Ratnam, Boise, ID (US);

Renato C. Padilla, Folsom, CA (US);

Peter Feeley, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0616 (2013.01); G06F 3/064 (2013.01); G06F 3/0652 (2013.01); G06F 3/0679 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/3495 (2013.01); G11C 2211/5641 (2013.01);
Abstract

The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.


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