The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2023
Filed:
Oct. 19, 2020
Applicant:
Stmicroelectronics, Inc., Coppell, TX (US);
Inventors:
Nicolas Loubet, Guilderland, NY (US);
Pierre Morin, Kessel-Lo, BE;
Assignee:
STMICROELECTRONICS, INC., Coppell, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/15 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 29/1054 (2013.01); H01L 29/155 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01);
Abstract
Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.