The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Dec. 02, 2020
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Siva P. Adusumilli, South Burlington, VT (US);

Mark Levy, Williston, VT (US);

Jeonghyun Hwang, Ithaca, NY (US);

Assignee:

GlobalFoundries U.S. Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/16 (2006.01); H01L 29/04 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7783 (2013.01); H01L 27/088 (2013.01); H01L 29/04 (2013.01); H01L 29/1602 (2013.01); H01L 29/2003 (2013.01); H01L 29/66462 (2013.01);
Abstract

Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.


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