The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

May. 11, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Min-Shin Wu, Hsinchu, TW;

Meng-Sheng Chang, Hsinchu, TW;

Shao-Yu Chou, Hsinchu, TW;

Yao-Jen Yang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/112 (2006.01); G11C 17/18 (2006.01); G11C 17/16 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01);
Abstract

A method of manufacturing an anti-fuse device includes forming an anti-fuse structure on a substrate, forming a first transistor at a first position away from the anti-fuse device in a first direction, and forming a second transistor at a second position away from the anti-fuse device in a second direction opposite the first direction. Forming the anti-fuse structure includes forming first and second S/D structures in an active area, the first transistor includes the first S/D structure, and the second transistor includes the second S/D structure. The method includes constructing a first electrical connection between gate structures of the first and second transistors and a second electrical connection between a third S/D structure of the first transistor and a fourth S/D structure of the second transistor.


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