The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Jun. 15, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Parth Amin, Fremont, CA (US);

Anubhav Khandelwal, San Jose, CA (US);

Assignee:

SanDisk Technologies LLC, Addison, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/28 (2006.01); G11C 16/34 (2006.01); G11C 16/24 (2006.01); G11C 16/30 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/0433 (2013.01); G11C 16/102 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01);
Abstract

The programming techniques include the step of providing a memory device that includes a plurality of memory cells that are divided into at least two groups including a first group and a second group. The first group includes memory cells that are coupled to full select gate drains (SGDs), and the second group includes memory cells that are coupled to partial SGDs. The method continues with the step of applying a programming voltage to a selected word line that includes at least one memory cell of the first group and at least one memory cell of the second group. Simultaneous to the application of the programming voltage, the method continues with applying voltages to bit lines coupled to memory cells. The voltages being determined based on if the memory cells are of the first group or are of the second group.


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